R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 467

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note:
Bit
8
7
6 to 4
3
2, 1
0
*
Bit Name
ENDIAN
BW

DLLEN

DCE
Depends on the setting of external pin (MODE5).
Undefined* R
Initial
Value
0
All 0
0
All 0
0
R/W
R/W
R
R/W
R
R/W
Description
Endian Identifier
Indicates whether big endian or little endian mode is
selected for the external data bus.
0: Little endian mode
1: Big endian mode
Bus Width
Specifies the DDR-SDRAM bus width.
This bit should always be cleared to 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
DLL Enable
Sets whether the DLL for generating the read timing for
the DDR-SDRAM is valid or invalid. When this bit is
set to 1, the DLL is enabled and read access to
memory is possible.
Reserved
These bits are always read as 0. The write value
should always be 0.
DDR Controller Enable
Enables or disables SDRAM control by the DDRIF.
0: Disables SDRAM control
1: Enables SDRAM control
Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 415 of 1286
REJ09B0158-0100