R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 914

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 23 Serial Protocol Interface (HSPI)
During the transmit function the slave responds by sending data to the master synchronized with
the HSPI_CLK from the master transmitted. Data from the slave is sampled and transferred to the
shift register in the module and on completion of the transmit function, is transferred to SPRBR.
The HSPI_CS pin is used to select the HSPI module when the HSPI is configured as a slave, and
prepare it to receive data from an external master. When the FBS bit in SPCR is 0, the HSPI_CS
pin must be driven high between successive bytes. When the FBS = 1, the HSPI_CS pin can stay
low for several byte transmissions. In this case, if the system is configured such that the FBS is
always 1, then the HSPI_CS line can be fixed at ground (if the HSPI will only be used as a slave).
23.4.2
The operation of the HSPI when DMA is used to perform transmit and receive data transfers is
simpler than when DMA is not used. The HSPI must be configured as in the case for transfers
without DMA. FIFO mode must be disabled. The DMA controller (DMAC) should then be
configured to transfer the required amount of data. DMA requests can then be enabled in the HSPI
module and the transfers will then take place without further processor intervention. When the
DMAC indicates that all transfers have ended then the DMA request signals in the HSPI module
should be disabled to remove any remaining DMA requests. This is necessary as the HSPI module
will always request data to transmit.
23.4.3
In order to reduce the interrupt overhead on the processor in the case for operation without DMA
mode, FIFO mode has been provided. When FIFO mode is enabled, up to 8 bytes can be written in
advance for transmission and up to 8 bytes can be received before the receive FIFO needs to be
read. To transfer the specified amount of data between the HSPI module and an external device,
follow the following procedure:
1. Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity
2. Write bytes into the transmit FIFO via SPTBR. If more than 8 bytes are to be transmitted then
3. Respond to the transmit FIFO halfway interrupt when it occurs by writing more data to the
4. When all of the transmit data has been written into the transmit FIFO, disable the transmit
5. Respond to the receive FIFO not empty interrupt until all the expected data has been received.
Rev.1.00 Dec. 13, 2005 Page 862 of 1286
REJ09B0158-0100
etc.) and enable FIFO mode.
enable the transmit FIFO halfway interrupt to keep track of the FIFO level as data is
transmitted.
transmit FIFO and reading data from the receive FIFO via SPRBR.
FIFO halfway interrupt and read the contents of the receive FIFO until it is empty. Enable the
receive FIFO not empty interrupt to keep track of when the final bytes of the transfer are
received.
Operation Overview with DMA
Operation with FIFO Mode Enabled