R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 470

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 DDR-SDRAM Interface (DDRIF)
12.4.3
STR specifies various timing parameters for the DDR-SDRAM.
Rev.1.00 Dec. 13, 2005 Page 418 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Initial value:
Initial value:
Bit
63 to 20 
19, 18
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
SDRAM Timing Register (STR)
Bit Name
WR
R/W
63
47
31
15



R
R
R
0
0
0
0
SRFC
R/W
62
46
30
14



R
R
R
0
0
0
0
R/W
61
45
29
13



R
R
R
0
0
0
0
Initial
Value
All 0
00
SWR
R/W
60
44
28
12



R
R
R
0
0
0
0
SRRD
R/W
R/W
R
R/W
59

43

27

11
R
R
R
0
0
0
0
R/W
58
42
26
10



R
R
R
0
0
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Minimum Number of Cycles from Write command to
Read Commands
These bits specify the minimum number of cycles
required by the SDRAM from the issuing of a WRITE
command to the issuing of a subsequent READ
command.
00: 3 cycles
01: 4 cycles
10: 5 cycles
11: 6 cycles
SRAS
R/W
57
41
25



R
R
R
0
0
0
9
0
R/W
56
40
24



R
R
R
0
0
0
8
0
R/W
55
39
23



R
R
R
0
0
0
7
0
SRC
R/W
54
38
22



R
R
R
0
0
0
6
0
R/W
53
37
21



R
R
R
0
0
0
5
0
R/W
52
36
20



R
R
R
0
0
0
4
0
R/W
SCL
R/W
51

35

19
R
R
0
0
0
3
0
WR
R/W
R/W
50
34
18


R
R
0
0
0
2
0
SRCD
R/W
R/W
49
33
17


R
R
0
0
0
1
0
RW
SRP
R/W
R/W
47
32
16


R
R
0
0
0
0
0