R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 214

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 Memory Management Unit (MMU)
Rev.1.00 Dec. 13, 2005 Page 162 of 1286
REJ09B0158-0100
Bit
17, 16
15 to 10
9
8
7 to 3
2
Bit Name

URC
SQMD
SV

TI
Initial
Value
All 0
All 0
0
0
All 0
0
R/W
R
R/W
R/W
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
UTLB Replace Counter
These bits serve as a random counter for indicating
the UTLB entry for which replacement is to be
performed with an LDTLB instruction. This bit is
incremented each time the UTLB is accessed. If URB
> 0, URC is cleared to 0 when the condition URC =
URB is satisfied. Also note that if a value is written to
URC by software which results in the condition of URC
> URB, incrementing is first performed in excess of
URB until URC = H'3F. URC is not incremented by an
LDTLB instruction.
Store Queue Mode Bit
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception
Single Virtual Memory Mode/Multiple Virtual Memory
Mode Switching Bit
When this bit is changed, ensure that 1 is also written
to the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode
Reserved
These bits are always read as 0. The write value
should always be 0.
TLB Invalidate Bit
Writing 1 to this bit invalidates (clears to 0) all valid
UTLB/ITLB bits. This bit is always read as 0.
in case of user access)