R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 595

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

After device 1 has claimed and granted the bus, and transferred data, the priority is as follows:
PCIC > device 0 > device 2 > device 3 > device 1
Then, after the PCIC has claimed and granted the bus, and transferred data, the priority is changed
to:
Device 0 > device 2 > device 3 > device 1 > PCIC
After device 3 has claimed and granted the bus, and transferred data, the priority is changed to:
Device 0 > device 2 > device 1 > PCIC > device 3
In host bus bridge mode, bus parking is always controlled by the PCIC.
(5)
• 10 interrupts are available (these signals are connected to the INTC of this LSI)
• Interrupts are enabled/disabled and their priority levels are specified by the INTC of this LSI
• When the PCIC operates normal mode, INTA output is available to the host device on the PCI
Table 13.6 Interrupt Priority
Signal
PCISERR
PCIINTA
PCIINTB
PCIINTC
PCIINTD
PCIEER
PCIPWD3
PCIPWD2
PCIPWD1
PCIPWD0
bus. The INTA pin is specified assert or negate by the IOCS bit in the PCICR.
Interrupts
Interrupt Source
SERR assertion detected in host bus bridge mode
PCI interrupt A (INTA) detected in host bus bridge mode
PCI interrupt B (INTB) detected in host bus bridge mode
PCI interrupt C (INTC) detected in host bus bridge mode
PCI interrupt D (INTD) detected in host bus bridge mode
Error on PCI bus occurs and reflected in PCIIR and PCIAINT. The
interrupt can be masked.
Power state transition to D3 caused by PCIPINT. The interrupt can
be masked.
Power state transition to D2 caused by PCIPINT. The interrupt can
be masked.
Power state transition to D1 caused by PCIPINT. The interrupt can
be masked.
Power state transition to D0 caused by PCIPINT. The interrupt can
be masked.
Rev.1.00 Dec. 13, 2005 Page 543 of 1286
Section 13 PCI Controller (PCIC)
REJ09B0158-0100
Priority
High
Low