R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 83

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1.7
The SH7780 includes an on-chip SuperHyway memory which stores instructions or data. The
SuperHyway memory has the following features.
• Capacity
• Memory address map
• Ports
• Access
• Minimum access time
• Usage note
Total SuperHyway memory capacity is 32 Kbytes (512 words
The SuperHyway memory is allocated within the physical address H'FE41 0000 to H'FE41
3FFF and H'FE42 0000 to H'FE42 3FFF.
Each page has one common read and write port, and is connected to the SuperHyway bus via a
4-stage buffer respectively. High-speed access to the SuperHyway memory is enabled by the
SuperHyway bus master.
The SuperHyway memory is always accessed by the SuperHyway bus master module,
including the CPU, via the SuperHyway bus which is a physical address bus.
1-/2-/4-/8-/16-/32-byte access is possible for both reading and writing
(with wraparound on 32-byte boundary data).
A 32-byte cache fill can be read out with one access
(an 8-byte × 4 transfer on the SuperHyway bus).
Note that the read/write operation on the SuperHyway bus is done with one clock. After that
the bus is released.
1-/2-/4-/8-byte read access: 14 clock cycles; 1-/2-/4-/8-byte write access: 12 clock cycles
16-/32-byte read access: 17 clock cycles; 16-/32-byte write access: 15 clock cycles
(The SuperHyway clock ≤ 200 MHz)
A SuperHyway bus master module, such as DMAC, can access the SuperHyway memory in
sleep mode.
SuperHyway Memory (SuperHyway RAM)
Rev.1.00 Dec. 13, 2005 Page 31 of 1286
×
256 bits
×
2 pages).
Section 1 Overview
REJ09B0158-0100