R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 449

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Local Bus State Controller (LBSC)
11.5.10 Bus Release and Acquire Sequence
The LBSC holds the bus itself unless it receives a bus request.
On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the LBSC
releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the
currently executing bus cycle ends. On receiving the BREQ negation (high level) indicating that
the slave has released the bus, the LBSC negates (drives high) the BACK signal and resumes use
of the bus.
The actual bus release sequence is as follows.
First, the bus use permission signal is asserted in synchronization with the rising edge of the clock.
The address bus and data bus go to the high-impedance state in synchronization from next rising
edge of the clock after this BACK assertion. At the same time, the bus control signals (BS, CSn,
WE, RD, R/W, CE2A, and CE2B) go to the high-impedance state. These bus control signals are
negated no later than one cycle before going to high-impedance. Bus request signal sampling is
performed on the rising edge of the clock.
The sequence for re-acquiring the bus from the slave is as follows.
As soon as BREQ negation is detected on the rising edge of the clock, BACK is negated and bus
control signal driving is started. Driving of the address bus and data bus starts at the next rising
edge of an in-phase clock. The bus control signals are asserted and the bus cycle is actually
started, at the earliest, at the clock rising edge at which the address and data signals are driven.
In order to reacquire the bus and start execution of bus access, the BREQ signal must be negated
for at least two cycles.
Using the LCKN bit in CHCR of the DMAC, it is possible to restrain the bus release in the cycle
between read and write access.
If a DMA transfer is executed for the space that the source and destination address are in the
LBSC space and the LCKN bit in CHCR is cleared to 0, the bus is not released in the cycle
between read and write accesses even if the bus release signal (BREQ) is asserted.
Rev.1.00 Dec. 13, 2005 Page 397 of 1286
REJ09B0158-0100