R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 82

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
1.6
SuperHyway Bus
The SH7780 is implemented with the SuperHyway bus as the system bus.
The SuperHyway bus is a 32-bit-address, 64-bit-data internal bus capable of up to 200 MHz
operation that is connected to on-chip modules to allow high speed communication.
Each module that is connected to the SuperHyway bus operates as an initiator (i.e. , bus master)
that issues a transfer request or a target that replies with a response to the request. The transaction
is controlled by the dedicated SuperHyway router.
The CPU, PCIC, and DMAC modules can all operate as an initiator. The LRU method is used to
decide the request priority of the SuperHyway bus mastership. The initial request priority order is:
CPU > DMAC > PCIC. The response priority level is fixed: peripheral modules* > DMAC > CPU
> SuperHyway RAM > LBSC > PCIC > DDRIF. Note that when using debugging function (H-
UDI emulator), the debugging functional module has the highest priority.
The transfer data size varies with each module. For details, refer to the corresponding section for
each module.
An actual transaction on the SuperHyway bus is started from a request issued by the initiator
module according to a read/write command sent to the SuperHyway bus address (physical
address), and then the target module replies with a response to the request (LOAD/STORE
transaction). In addition, a transaction that controls the cache coherency occurs if necessary
(FLUSH/PURGE transaction). Note that these transactions are done automatically by the
SuperHyway modules, so they cannot be explicitly issued by software.
Note: "Peripheral modules" means modules that are connected to the peripheral bus (except for
the INTC and DMAC modules).
Rev.1.00 Dec. 13, 2005 Page 30 of 1286
REJ09B0158-0100