R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 702

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Power-Down Mode
17.6
17.6.1
To preserve the contents of the DDR-SDRAM with battery backup, make sure that the DDR-
SDRAM is in the self-refresh mode before turning off the system power supply. When the system
power supply is turned on, whether initialization of the DDR-SDRAM and cancellation of the self-
refresh mode is needed will depend on whether the DDR-SDRAM has been in self-refresh mode
or has not been initialized. Both a transition to and a cancellation of the self-refresh mode are done
for the DDR-SDRAM by a command.
RMODE Bit: Bit 33 in MIM. The initial value is 0. Setting this bit to 1 after setting the DRE bit
in MIM to 1 causes the DDRIF to start the sequence for a transition to the self-refresh mode. For
details, see section 12.5.5 (1), Self-Refresh Mode.
SMS Bits: Bits 2 to 0 in SCR. SMS = B'011. These bits are used to assert the CKE signal (high)
and to cancel the self-refresh mode with the DESL command.
BKPRST Signal: To prevent the CKE signal from being unstable when turning on or off the LSI
power supply, the BKPRST signal must be driven to low in synchronization with turning the LSI
power supply on or off. The BKPRST signal must be kept low while the system power supply is
turned off.
Rev.1.00 Dec. 13, 2005 Page 650 of 1286
REJ09B0158-0100
PRESET
DDRIF reset
VDD, VDDQ
(1.25 V, 3.3 V)
CKE
BKPRST
DDR-SDRAM Power Supply Backup
Self-Refresh and Initialization
Transition to self-refresh
mode completed
Figure 17.1 DDR-SDRAM Interface Operation when
min 0 ms
Turning System Power Supply On/Off
min 1 ms
System power
turned off
supply
System power
turned on
supply
Power-on
canceled
reset
Delay time of
LSI internal reset
min 0 ms
by SMS bits in SCR
CKE asserted