R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 397

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
11
10 to 8
7
6 to 4
Bit Name

WTH

BSH
Initial
Value
0
111
0
000
R/W
R
R/W
R
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
WE Hold Cycle (WE Negation–CSn Negation Delay
Cycle)
Specify the number of cycles to be inserted from WE
negation to CSn negation. (Available only when the
SRAM interface, byte control SRAM interface, or burst
ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
BS Hold Cycle
Specify the number of cycles for the BS assertion. Total
access cycle number is not change by setting these
bits. This setting is valid when CSn assertion-RD or -
WE assertion delay cycle (RDS or WTS setting) is set
to 1 or more.
000: BS assertion is 1 cycle
001: BS assertion is 2 cycle
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 345 of 1286
REJ09B0158-0100