R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1179

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29.4
By using the user break debugging support function, the branch destination address can be
modified when the CPU accepts the user break request. Specifically, setting the UBDE bit of
break control register CBCR to 1 allows branching to the address indicated by DBR instead of
branching to the address indicated by the [VBR + offset]. Figure 29.2 shows the flowchart of the
user break debugging support function.
Hardware operations
User Break Debugging Support Function
Debugging program
(STC instruction)
Figure 29.2 Flowchart of User Break Debugging Support Function
R15 ← SGR
PC ← DBR
Yes
EXPEVT ← Exception code
(CBCR.UBDE == 1)
&& (user break)?
Exception
No
Exception handling routine
INTEVT ← Interrupt code
Exception operation ends
PC
Exception/interrupt/trap?
Execute RTE instruction
Exception/interrupt
←
Reset exception?
SR.MD ← B'1
SR.RB ← B'1
SR.BL ← B'1
VBR +
is generated
SGR ← R15
PC ← SPC
SR ← SSR
SPC ← PC
SSR ← SR
No
vector offset
Interrupt
Rev.1.00 Dec. 13, 2005 Page 1127 of 1286
Section 29 User Break Controller (UBC)
Yes
TRA ← TRAPA (imm)
Trap
PC ← H'A000 0000
EXPEVT ← H'160
REJ09B0158-0100