R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 925

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24.3.3
OPCR is an 8-bit readable/writable register that aborts command operation, and suspends or
continues data transfer.
Bit
7
6
5
Operation Control Register (OPCR)
Bit Name
CMDOFF
—
RD_CONTI 0
Initial value:
Initial
Value
0
0
R/W:
Bit:
CMD
OFF
R/W
7
0
R/W
R/W
R
R/W

6
0
R
Description
Command Off
Aborts all command operations (MMCIF command
sequence) when 1 is written after a command is
transmitted. This bit is cleared automatically after the
MMCIF received the CMDOFF command.
Write enabled period: From command transmission
completion to command sequence end
Write of 0: Operation is not affected.
Write of 1: Command sequence is forcibly aborted.
Note: Do not write to this bit out of the write enable
Reserved
This bit is always read as 0. The write value should
always be 0.
Read Continue
Read data reception is resumed when 1 is written while
the sequence has been halted by FIFO full or
termination of block reading in multiple block read.
This bit is cleared automatically when 1 is written and
the MMCIF received the RD_CONTI command.
Write enabled period: While read data reception is
halted
Write of 0: Operation is not affected.
Write of 1: Resumes read data reception.
Note: Do not write to this bit out of the write enable
CONTI
R/W
RD_
5
0
DATAEN
period.
period.
R/W
4
0

Section 24 Multimedia Card Interface (MMCIF)
R
3
0
Rev.1.00 Dec. 13, 2005 Page 873 of 1286

2
0
R

R
1
0

R
0
0
REJ09B0158-0100