R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 649

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bus Modes: There are two bus modes: cycle steal mode and burst mode. Select the mode in the
TB and LCKN bits in CHCR. Moreover, cycle steal mode has normal and intermittent modes that
are specified by the CMS bits in DMAOR.
• Cycle-Steal Mode
 Normal mode1 (DMAOR.CMS = 00, CHCR.LCKN = 0, CHCR.TB = 0)
Figure 14.6 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
 Normal mode 2 (DMAOR.CMS = 00, CHCR.LCKN = 1, CHCR.TB = 0)
In cycle-steal normal mode, the SuperHyway bus mastership is given to another bus master
after a one-transfer unit (byte, word, longword, 16-byte, or 32-byte unit) DMA transfer.
When the next transfer request occurs, the DMAC issues the next transfer request, the bus
mastership is obtained from the other bus master and a transfer is performed for one-
transfer unit. When that transfer ends, the bus mastership is passed to the other bus master.
This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the
transfer request source, transfer source, and transfer destination.
In cycle steal normal mode 2, the DMAC does not keep the SuperHyway bus mastership, is
to obtain the bus mastership in every one transfer unit of read or write cycle.
Figure 14.7 shows an example of DMA transfer timing in cycle steal normal mode 2.
Figure 14.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1
DREQ
SuperHyway
bus cycle
CPU
CPU
(DREQ Low Level Detection)
CPU
DMAC DMAC
Read/Write
Bus mastership returned to CPU once
Section 14 Direct Memory Access Controller (DMAC)
CPU
Rev.1.00 Dec. 13, 2005 Page 597 of 1286
DMAC
Read/Write
DMAC
CPU
REJ09B0158-0100