R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 743

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.4
The CMT has two operation modes: one is four channels free-running timer that operates with the
common time base of 32-bit free-running timer operating between approximately 1.5MHz (Pck/32
selected at Pck = 50MHz) to 30kHz (Pck/1024 selected at Pck = 33MHz). The other is 16-bit
timer/counter that operating as two channels 16-bit timer/counter and two channels 16-bit timer.
When operating as the timer, it can be selectable input capture or output compare. They differ
from the free-running timer mode that they are initialized to H'0000 when capture input or
compare match occurs on that channel.
19.4.1
The timers and counters are based on edge detection on the input pins. An active edge can be
selectable by setting CMTCFG to be a rising edge, falling edge, or both edges. In addition, the
edge detection logic can operate in rotary switch operation where the combination of two inputs
indicates whether the switch has been turned right or left and the updown counter is incremented
or decremented. The edge detection input can either work independently for the timers or the up-
counters or can work as pairs to indicate up and down to the updown-counters.
In order for an edge to be detected, the input pulse to the CMT_CTR pin must last for at least two
cycles of the clock divided from the peripheral clock (Pck) for that channel, as shown in figure
19.2.
Operation
Edge Detection
Pck
The clock divided
from Pck
Input pulse
Edge detection
Figure 19.2 Edge Detection (example of rising edge)
Rev.1.00 Dec. 13, 2005 Page 691 of 1286
Section 19 Compare Match Timer (CMT)
REJ09B0158-0100