R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 609

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI includes the direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (DMA transfer end notification), external memory, on-chip memory,
memory-mapped external devices, and peripheral modules.
14.1
• Twelve channels (four channels can receive an external request: channel 0 to 3)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), 16 bytes, and 32
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode
• Transfer requests:
• Selectable bus modes:
• Selectable channel priority levels:
• Interrupt request: An interrupt request can be generated to the CPU after half of the transfers
• External request detection: There are following four types of DREQn input detection.
• Transfer end notification signal:
bytes
External request (channel 0 to 3), peripheral module request (channel 0 to 5), or auto request
can be selected.
The following modules can issue an peripheral module request.
 SCIF0, SCIF1, HAC, HSPI, SIOF, SSI, FLCTL, and MMCIF
Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
The channel priority levels are selectable between fixed mode and round-robin mode.
ended, all transfers ended, or an address error occurred.
(n = 0 to 3)
 Low level detection (Initial value)
 High level detection
 Rising edge detection
 Falling edge detection
Active levels for both DACKn and DRAKn can be set independently.
(n = 0 to 3, Initial value: low active)
Section 14 Direct Memory Access Controller (DMAC)
Features
Section 14 Direct Memory Access Controller (DMAC)
Rev.1.00 Dec. 13, 2005 Page 557 of 1286
REJ09B0158-0100