R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1269

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

A.
The CPUOPM is used to control the CPU operation mode. This register can be read from or
written to the address H'FF2F 0000 in P4 area or H'1F2F 0000 in area 7 as 32-bit size. The write
value to the reserved bits should be the initial value. The operation is not guaranteed if the write
value is not the initial value.
The CPUOPM register should be updated by the CPU store instruction not the access from
SuperHyway bus master except CPU.
After the CPUOPM is updated, read CPUOPM once, and execute one of the following two
methods.
1. Execute a branch using the RTE instruction.
2. Execute the ICBI instruction for any address (including non-cacheable area).
After one of these methods are executed, it is guaranteed that the CPU runs under the updated
CPUOPM value.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
CPU Operation Mode Register (CPUOPM)
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
28
12
R
R
0
0
27
11
R
0
R
0
26
10
R
R
0
0
Appendix
25
R
R
0
9
1
24
R
R
0
8
1
23
R
R
0
7
1
Rev.1.00 Dec. 13, 2005 Page 1217 of 1286
22
R
R
0
6
1
RABD
R/W
21
R
0
5
1
20
R
R
0
4
0
INTMU
R/W
19
R
0
3
0
REJ09B0158-0100
18
R
R
0
2
0
17
R
R
0
1
0
Appendix
16
R
R
0
0
0