R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 234
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Memory Management Unit (MMU)
9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and
Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve
the data TLB protection violation, execute the exception handling return instruction (RTE),
terminate the exception handling routine, and return control to the normal flow. The RTE
instruction should be issued at least one instruction after the LDTLB instruction.
7.5.7
An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains
address translation information matching the virtual address to which a data access (write) is
made, and the access is permitted. The initial page write exception processing carried out by
hardware and software is shown below.
Hardware Processing: In the event of an initial page write exception, hardware carries out the
following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'080 in EXPEVT.
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and
Software Processing (Initial Page Write Exception Handling Routine): Software is responsible
for the following processing:
1. Retrieve the necessary page table entry from external memory.
2. Write 1 to the D bit in the external memory page table entry.
3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table
Rev.1.00 Dec. 13, 2005 Page 182 of 1286
REJ09B0158-0100
starts the data TLB protection violation exception handling routine.
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
saved in SGR.
starts the initial page write exception handling routine.
entry recorded in external memory.
Initial Page Write Exception
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