R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 683
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 683 of 1342
- Download datasheet (7Mb)
16.3.3
WDTBST is a readable/writable 32-bit register that clears WDTBCNT. Use a longword write
access to clear the WDTBCNT, with H'55 in the bits 31 to 24. The reading value of this register is
always H'00.
Initial value:
Initial value:
Bit
5
4
3
2 to 0
R/W:
R/W:
Bit:
Bit:
Watchdog timer Base Stop Time Register (WDTBST)
Bit Name
RSTS
WOVF
IOVF
R/W
31
15
R
0
0
R/W
30
14
R
0
0
R/W
29
13
R
0
0
Initial
Value
0
0
0
R
(Given code)
R/W
28
12
R
0
0
R/W
R/W
R/W
R/W
R/W
All 0
27
11
R
0
0
R/W
26
10
R
0
0
Description
Reset Select
Specifies the kind of reset to be performed when
WDTCNT overflows in watchdog timer mode. This
setting is ignored in interval timer mode.
0: Power-on reset
1: Manual reset
Watchdog Timer Overflow Flag
Indicates that WDTCNT has overflowed in watchdog
timer mode. This flag is not set in interval timer mode.
0: An overflow has not occurred
1: An overflow on WDTCNT has occurred
Interval Timer Overflow Flag
Indicates that WDTCNT has overflowed in interval
timer mode. This flag is not set in watchdog timer
mode.
0: An overflow has not occurred
1: An overflow on WDTCNT has occurred
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25
R
0
9
0
R/W
24
R
0
8
0
23
R
R
0
7
0
Rev.1.00 Dec. 13, 2005 Page 631 of 1286
22
R
R
0
6
0
Section 16 Watchdog Timer and Reset
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
REJ09B0158-0100
18
R
R
0
2
0
17
R
R
0
1
0
16
R
R
0
0
0
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