R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 915
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 915 of 1342
- Download datasheet (7Mb)
6. Disable the module until it is required again.
In some applications, an undefined amount of data will received from an external HSPI device. If
this is the case, follow the following procedure:
1. Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity
2. Fill the transmit FIFO with the data to transmit. Enable the receive FIFO not empty interrupt.
3. Respond to the receive FIFO not empty interrupt and read data from the receive FIFO until it is
4. Disable the module when the transfer is to stop.
23.4.4
The following diagrams explain the timing relationship of all shift and sample processes in the
HSPI. Figure 23.3 shows the conditions when FBS = 0, while figure 23.4 shows the conditions
when FBS = 1. It can be seen that if CLKP in SPCR is 0 then transmit data is shifted on the falling
edge of HSPI_CLK and receive data is sampled on the rising edge. The opposite is true when
CLKP = 1.
etc.) and enable FIFO mode.
empty. Write more data to the transmit FIFO if required.
Timing Diagrams
sck_cycle
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
HSPI_TX
HSPI_RX
HSPI_CS
Figure 23.3 Timing Conditions when FBS = 0
MSB
MSB
1
2
6
6
3
5
5
4
4
4
5
3
3
Section 23 Serial Protocol Interface (HSPI)
Rev.1.00 Dec. 13, 2005 Page 863 of 1286
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REJ09B0158-0100
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