R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 315

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Interrupt mask register 2 (INTMSK2)
INTMSK2 settings are valid for particular IRL interrupt codes generated by the pattern of input
signals on pins IRL7 to IRL4 or IRL3 to IRL0 and when all IRL interrupts from the corresponding
set of pins are not masked by the setting in INTMSK1.
Initial value:
Initial value:
Bit
31
30
29
28
27
26
25
24
R/W:
R/W:
Bit:
Bit:
Name
IM015
IM014
IM013
IM012
IM011
IM010
IM009
IM008
IM015 IM014
IM115 IM114
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
IM013
IM113
R/W
R/W
29
13
0
0
Initial
Value
0
0
0
0
0
0
0
0
IM012
IM112
R/W
R/W
28
12
0
0
IM011
IM111
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
27
11
0
0
IM010
IM110
R/W
R/W
26
10
0
0
Description
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LLLL (H'0).
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LLLH (H'1).
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LLHL (H'2).
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LLHH (H'3).
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LHLL (H'4).
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LHLH (H'5).
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LHHL (H'6).
Sets masking of interrupt-
request generation by IRL3
to IRL0 = LHHH (H'7).
IM009
IM109
R/W
R/W
25
0
9
0
IM008
IM108
R/W
R/W
24
0
8
0
IM007
IM107
R/W
R/W
23
0
7
0
IM006
IM106
Rev.1.00 Dec. 13, 2005 Page 263 of 1286
R/W
R/W
22
0
6
0
Section 10 Interrupt Controller (INTC)
IM005
IM105
R/W
R/W
21
0
5
0
IM004
IM104
[When reading]
0: The interrupt is
1: The interrupt is
[When writing]
0: No effect
1: Masks the interrupt
R/W
R/W
20
0
4
0
acceptable.
masked.
IM003
IM103
R/W
R/W
19
0
3
0
IM002
IM102
REJ09B0158-0100
R/W
R/W
18
0
2
0
IM001
IM101
R/W
R/W
17
0
1
0
16


R
R
0
0
0