R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 421

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

CSn
R/W
RD
(read)
D31 to D0
(read)
WE
(write)
D31-D0
(ADS = 0)
(write)
D31-D0
(ADS = 1 to 7)
(write)
CLKOUT
A25 to A0
BS
Figure 11.10 SRAM Interface Wait Timing (Read-Strobe Negate Timing Setting)
Notes: 1. When CSnBCR RDSPL is set to 1.
2. When CSnWCR.BSH is set to 1.
TAS1:
Address Setup cycle
CSnWCR.ADS (0 to 7 cycles)
TAS1:
Address Setup cycle
CSnWCR.ADS (0 to 7 cycles)
T
CLKOUT
AS1
T
1
TS1:
CSn assertion-RD assertion
delay cycle (RD Setup cycle)
CSnWCR.RDS (0 to 7 cycles)
TS1:
CSn assertion-WE assertion delay cycle
(WE Setup cycle)
CSnWCR.WTS (0 to 7 cycles)
T
S1
*2
T
W
T
W
TW:
Insert wait cycle
CSnWCR.IW (0 to 25 cycles)
TW:
Insert wait cycle
CSnWCR.IW (0 to 25 cycles)
CLKOUT
T
W
T
W
Section 11 Local Bus State Controller (LBSC)
T
Rev.1.00 Dec. 13, 2005 Page 369 of 1286
2
TH1,TH2:
RD Negation-CSn Negation
delay cycle (RD Hold cycle)
CSnWCR.RDH (0 to 7 cycles)
T
H1
*1
TH1,TH2:
WE Negation-CSn Negation delay cycle
(WE Hold cycle)
CSnWCR.WTH (0 to 7 cycles)
T
H2
TAH1:
Address Hold cycle
CSnWCR.ADH (0 to 7 cycles)
T
TAH1:
Address Hold cycle
CSnWCR.ADH
(0 to 7 cycles)
AH1
REJ09B0158-0100