R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 480

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 DDR-SDRAM Interface (DDRIF)
3. The STR settings do not establish a relationship between the timing of the PREALL and REFA
4. Make the SDRAM enter the self-refresh state by setting the DRE and RMODE bits in MIM to
5. The DDRIF automatically issues the self-refresh command and sets the CKE pin low. The
6. Read the SELFS status bit in MIM to check whether or not the SDRAM has actually entered
[Return from self-refresh state]
1. Clear the RMODE and DRE bits in MIM to 0 to take the DDS-SDRAM out of the self-refresh
2. Read the SELFS status bit in MIM to check whether or not the SDRAM has actually returned
3. After allowing the time required for recovery from the self-refresh state, set registers so that
4. When access becomes possible, use the SMS bits in SCR to issue the REFA (auto-refresh)
5. Dummy read a byte from any SDRAM address.
6. Use the SMS bits in SCR to issue the PREALL (all-bank precharge) command.
7. Use the SMS bits in SCR to issue the REFA command. This operation is required to make the
8. Set MIM so that the counter for the auto-refresh function starts counting and thus drives auto-
(2)
Clearing or setting the PCKE bit in MIM changes the level of the CKE pin, the SDRAM enters or
leaves the power-down mode. The SDRAM in this mode consumes less power.
Since the SDRAM is made to enter the power-down mode after each round of memory access and
has to leave the power-down mode before each round of memory access, an overhead of one cycle
of the MCLK is incurred in each case.
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commands that are issued by using SCR. A period of waiting that is suitable for the memory
unit must be inserted.
1 (in this case, the value of the DCE bit should be left at 1).
SDRAM then automatically enters the self-refresh mode.
the self-refresh mode.
state.
from the self-refresh mode.
auto-refreshing is performed at an appropriate interval. After the recovery, wait for the time
required by the SDRAM before accessing the SDRAM (the time depends on the DDR-
SDRAM; for example, the requirements might be for 130 ns before issuing a command other
than a read command, and 200 clock cycles before issuing a read command).
command so that all memory rows are refreshed.
delay adjustment unit in the DDRIF operate.
refreshing at a regular interval. After this, normal memory access is possible.
Power-Down Mode (when CKE Goes Low)