R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 937

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24.3.7
CLKON controls the transfer clock frequency and clock ON/OFF.
At this time, use a sufficiently slow clock for transfer through open-drain type output in MMC
mode.
In a command sequence, do not perform clock ON/OFF or frequency modification.
Bit
7
6 to 4
3
2
1
0
Transfer Clock Control Register (CLKON)
Bit Name
CLKON
—
CSEL3
CSEL2
CSEL1
CSEL0
Initial value:
Initial
Value
0
All 0
0
0
0
0
R/W:
Bit:
CLKON
R/W
7
0
R/W
R/W
R
R/W
R/W
R/W
R/W

6
0
R
Description
Clock On
0: Fixes the transfer clock output from the MCCLK pin
1: Outputs the transfer clock from the MCCLK pin.
Reserved
These bits are always read as 0. The write value
should always be 0.
Transfer Clock Frequency Select
Note: To output transfer clock, it is necessary to set the
0000: Reserved
0001: Uses the 1/2-divided peripheral clock as a transfer clock.
0010: Uses the 1/4-divided peripheral clock as a transfer clock.
0011: Uses the 1/8-divided peripheral clock as a transfer clock.
0100: Uses the 1/16-divided peripheral clock as a transfer clock.
0101: Uses the 1/32-divided peripheral clock as a transfer clock.
0110: Uses the 1/64-divided peripheral clock as a transfer clock.
0111: Uses the 1/128-divided peripheral clock as a transfer clock.
1000: Uses the 1/256-divided peripheral clock as a transfer clock.
1001 to 1111: Setting prohibited

R
5
0
to low level.
CLKON bit to 1, and set the CSEL[3:0] bits other
than 0000 and 1001 to 1111.

4
0
R
CSEL3
R/W
Section 24 Multimedia Card Interface (MMCIF)
3
0
CSEL2 CSEL1 CSEL0
Rev.1.00 Dec. 13, 2005 Page 885 of 1286
R/W
2
0
R/W
0
1
R/W
0
0
REJ09B0158-0100