R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 350

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 Interrupt Controller (INTC)
Table 10.11 IRL[3:0], IRL[7:4] Pins and Interrupt Levels
IRL interrupt detection requires a built-in noise-cancellation feature; that is, a mechanism to
ensure that transient level changes on the IRL pins are not detected as interrupts. For this purpose,
an IRL interrupt is not detected unless the levels sampled per bus-clock cycle remain unchanged
for four consecutive cycles.
The IRL interrupt priority level should be maintained until the CPU has accepted the interrupt and
started interrupt exception handling. It is possible to change the priority level to a higher priority.
When IRL level-encoded interrupts have been selected, usage or non-usage of the holding function
for interrupt requests can be selected by clearing or setting the LSH bit in ICR0. When usage of
the holding function has been selected (ICR0.LSH = 0), interrupt requests are held in the detection
circuit and the interrupt request must be cleared in the exception handling routine after acceptance
of the interrupt. For details, refer to section 10.7 Usage Notes. To select non-usage of the holding
function, set the LSH bit in ICR0 to 1. In this case, the operation of IRL level detection provides
upward compatibility with the level-encoded IRL interrupts on current SH-4 products.
Rev.1.00 Dec. 13, 2005 Page 298 of 1286
REJ09B0158-0100
IRL3 or
IRL7
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
High
IRL2 or
IRL6
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
High
High
High
High
IRL1 or
IRL5
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
IRL0 or
IRL4
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Interrupt
Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request

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