R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 740

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Compare Match Timer (CMT)
19.3.4
CMTIRQS, once set, can only be cleared by a write. Writing 0 to these bits clears the interrupt
status bits. These conditions only create an interrupt if the relevant interrupt enable bit is set.
Rev.1.00 Dec. 13, 2005 Page 688 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 12 —
11
10
9
8
7
6
5
4
3, 2
1
0
R/W:
R/W:
Bit:
Bit:
Interrupt Status Register (CMTIRQS)
Bit Name
IO3
IO2
IO1
IO0
IC3
IC2
IC1
IC0
—
IE1
IE0
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
29
13
—
—
R
R
0
0
All 0
Initial
Value
All 0
0
0
0
0
0
0
0
0
0
0
28
12
—
—
R
R
0
0
R/W
IO3
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
27
—
11
R
0
0
R/W
IO2
26
10
—
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Channel 3 to 0 Interrupt Overflow
A bit for each channel indicates if the up-counters or
updown-counters have wrapped i.e. overflowed from
H'FFFF to H'0000 or underflowed from H'0000 to
H'FFFF.
0: The counter is not overflowed or underflowed
1: The counter is overflowed or underflowed
Channel 3 to 0 Interrupt Compare
A bit for each channel indicates whether in timer mode,
the free-running timer has become equal to the channel
times.
0: Timer has not become equal to the channel time
1: Timer has become equal to the channel time value
Reserved
These bits are always read as 0. The write value should
always be 0.
Channel 1 to 0 Interrupt Edge
A bit for each channel indicates whether an edge that
will cause an action (active edge) has been defected.
0: Channel 1 to 0 has not received an active edge
1: Channel 1 to 0 has received an active edge
R/W
IO1
25
—
value
R
0
9
0
R/W
IO0
24
—
R
0
8
0
R/W
IC3
23
—
R
0
7
0
R/W
IC2
22
—
R
0
6
0
R/W
IC1
21
—
R
0
5
0
R/W
IC0
20
—
R
0
4
0
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
R/W
IE1
17
—
R
0
1
0
R/W
IE0
16
—
R
0
0
0