R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1014
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 25 Audio Codec Interface (HAC)
25.3.3
HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the
command data to HACCSDR. The HAC then transmits the data to the codec via slot 2.
After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received
via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related
codec register address.
Rev.1.00 Dec. 13, 2005 Page 962 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3 to 0
R/W:
R/W:
Bit:
Bit:
Command/Status Data Register (HACCSDR)
CD11/
Bit Name
CD15/SD15
CD14/SD14
CD13/SD13
CD12/SD12
CD11/SD11
CD10/SD10
CD9/SD9
CD8/SD8
CD7/SD7
CD6/SD6
CD5/SD5
CD4/SD4
CD3/SD3
CD2/SD2
CD1/SD1
CD0/SD0
SD11
R/W
31
15
R
0
0
CD10/
SD10
R/W
30
14
R
0
0
CD9/
SD9
R/W
29
13
R
0
0
Initial
Value
All 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
All 0
CD8/
SD8
R/W
28
12
R
0
0
CD7/
SD7
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
27
11
R
0
0
CD6/
R/W
SD6
26
10
R
0
0
Description
Reserved
Always 0 for read and write.
Command Data 15 to 0/Status Data 15 to 0
Write data to these bits and then write the codec
register address in HACCSAR. The HAC then transmits
the data to the codec.
Read these bits to get the contents of the codec register
indicated by HACCSAR.
Reserved
Always 0 for read and write.
CD5/
SD5
R/W
25
R
0
9
0
CD4/
SD4
R/W
24
R
0
8
0
CD3/
SD3
R/W
23
R
0
7
0
CD2/
SD2
R/W
22
R
0
6
0
CD1/
SD1
R/W
21
R
0
5
0
CD0/
SD0
R/W
20
R
0
4
0
CD15/
SD15
R/W
19
R
0
0
3
CD14/
SD14
R/W
18
R
0
2
0
CD13/
SD13
R/W
17
R
0
1
0
CD12/
SD12
R/W
16
R
0
0
0
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