R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 844

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
21.5
SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources in each channel: transmit-FIFO-data-empty interrupt (TXI)
request, receive-error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and
break interrupt (BRI) request.
Table 21.7 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
If the TDFE flag in SCFSR is set to 1 when a TXI interrupt is enabled by the TIE bit, a TXI
interrupt request and a transmit-FIFO-data-empty request for DMA transfer are generated. If the
TDFE flag is set to 1 when a TXI interrupt is disabled by the TIE bit, only a transmit-FIFO-data-
empty request for DMA transfer is generated. A transmit-FIFO-data-empty request can activate
the DMAC to perform data transfer.
If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit, an
RXI interrupt request and a receive-FIFO-data-full request for DMA transfer are generated. If the
RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit, only a receive-FIFO-
data-full request for DMA transfer is generated. A receive-FIFO-data-full request can activate the
DMAC to perform data transfer. Note that generation of an RXI interrupt request or a receive-
FIFO-data-full request by setting the DR flag to 1 occurs only in asynchronous mode.
When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is
generated. If transmission/reception is carried out using the DMAC, set and enable the DMAC
before making the SCIF settings. Also make settings to inhibit output of RXI and TXI interrupt
requests to the interrupt controller. If output of interrupt requests is enabled, these interrupt
requests to the interrupt controller can be cleared by the DMAC regardless of the interrupt handler.
By setting the REIE bit to 1 while the RIE bit is cleared to 0 in SCSCR, it is possible to output
ERI interrupt requests, but not RXI interrupt requests.
Rev.1.00 Dec. 13, 2005 Page 792 of 1286
REJ09B0158-0100