R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 811

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.3.9
SCFCR performs data count resetting and trigger data number setting for transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
Initial value:
Bit
15 to 11
10
9
8
Note: * Reserved bit in channel 1.
R/W:
Bit:
FIFO Control Register n (SCFCR)
Bit Name
—
RSTRG2*
RSTRG1*
RSTRG0*
15

R
0
14

R
0
13

R
0
Initial
Value
All 0
0
0
0
12

R
0
11

R
0
R/W
R
R/W
R/W
R/W
RST
RG2*
R/W
10
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SCIF0_RTS Output Active Trigger
The SCIF0_RTS signal becomes high when the
number of receive data stored in SCFRDR exceeds the
trigger number shown below.
000:63
001:1
010:8
011:16
100:32
101:48
110:54
111:60
Section 21 Serial Communication Interface with FIFO (SCIF)
R/W
RST
RG1*
9
0
R/W
RST
RG0*
8
0
RTRG1
R/W
7
0
RTRG0
Rev.1.00 Dec. 13, 2005 Page 759 of 1286
R/W
6
0
TTRG1
R/W
5
0
TTRG0
R/W
4
0
MCE*
R/W
3
0
REJ09B0158-0100
TFCL
R/W
2
0
RFCL
R/W
1
0
LOOP
R/W
0
0