R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 875
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 875 of 1342
- Download datasheet (7Mb)
22.3.11 Transmit Data Assign Register (SITDAR)
SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a
frame.
Initial value:
Bit
15
14 to 12 —
11 to 8
7
6
R/W:
Bit:
Bit Name
TDLE
TDLA[3:0]
TDRE
TLREP
TDLE
R/W
15
0
14
—
R
0
13
—
R
0
Initial
Value
0
All 0
0000
0
0
12
—
R
0
R/W
R/W
R/W
R
R/W
R/W
R/W
11
0
R/W
TDLA[3:0]
10
0
Transmit Right-Channel Data Enable
Description
Transmit Left-Channel Data Enable
0: Disables left-channel data transmission
1: Enables left-channel data transmission
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a transmit
frame as 0000 (0) to 1110 (14).
1111: Setting prohibited
•
0: Disables right-channel data transmission
1: Enables right-channel data transmission
Transmit Left-Channel Repeat
0: Transmits data specified in the SITDR bit in SITDR
1: Repeatedly transmits data specified in the SITDL bit
•
•
R/W
as right-channel data
in SITDR as right-channel data
9
0
Transmit data for the left channel is specified in the
SITDL bit in SITDR.
This bit setting is valid when the TDRE bit is set to
1.
When this bit is set to 1, the SITDR settings are
ignored.
R/W
8
0
TDRE
R/W
7
0
TLREP
Rev.1.00 Dec. 13, 2005 Page 823 of 1286
R/W
6
0
Section 22 Serial I/O with FIFO (SIOF)
—
R
5
0
—
R
4
0
R/W
3
0
REJ09B0158-0100
TDRA[3:0]
R/W
2
0
R/W
1
0
R/W
0
0
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