R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 261

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5. Cache miss (with write-back)
8.3.3
When the Operand cache (OC) is enabled (OCE = 1 in CCR) and data is written to a cacheable
area, the cache operates as follows:
1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual
2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting
• If there is a way whose tag matches and its V bit is 1, see No. 3 for copy-back and No. 4 for
• I If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is
• If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is
3. Cache hit (copy-back)
4. Cache hit (write-through)
The tag and data field of the cache line on the way which is selected to replace are saved in the
write-back buffer. Then data is read into the cache line on the way which is selected to replace
from the physical address space corresponding to the virtual address. Data reading is
performed, using the wraparound method, in order from the quad-word data (8 bytes)
including the cache-missed data. In the prefetch operation the CPU doesn't wait the data
arrives. While the one cache line of data is being read, the CPU can execute the next
processing. And the LRU bits are updated to indicate the way is latest one. The data in the
write-back buffer is then written back to external memory.
address bits [12:5].
from virtual address translation by the MMU:
write-through.
selected to replace using the LRU bits is 0, see No. 5 for copy-back and No. 7 for write-
through.
selected to replace using the LRU bits is 1, see No. 6 for copy-back and No. 7 for write-
through.
A data write in accordance with the access size is performed for the data field on the hit way
which is indexed by virtual address bits [4:0]. Then 1 is written to the U bit. The LRU bits are
updated to indicate the way is the latest one.
A data write in accordance with the access size is performed for the data field on the hit way
which is indexed by virtual address bits [4:0]. A write is also performed to external memory
corresponding to the virtual address. Then the LRU bits are updated to indicate the way is the
latest one. In this case, the U bit isn't updated.
Write Operation
Rev.1.00 Dec. 13, 2005 Page 209 of 1286
Section 8 Caches
REJ09B0158-0100