R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 376

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 11 Local Bus State Controller (LBSC)
11.3.2
The memory bus width of the LBSC can be set independently for each area. For area 0, a bus
width of 8, 16, or 32 bits is set according to the external pin settings at a power-on reset by the
PRESET pin. The correspondence between the external pins (MODE 4 and MODE 3) and the bus
width at a power-on reset is shown below.
Table 11.3 Correspondence Between External Pins (MODE4 and MODE3)
When either the SRAM or ROM interface is used in areas 1 to 2 and 4 to 6, a bus width of 8, 16,
or 32 bits can be selected through the CSn bus control register (CSnBCR). When the burst ROM
interface is used, a bus width of 8, 16, or 32 bits can be selected. When the byte-control SRAM
interface is used, a bus width of 16 or 32 bits can be selected. When the MPX interface is used, a
bus width of 32 bits should be selected.
When using the PCMCIA interface, a bus width of 8 or 16 bits should be selected. For details, see
section 11.5.5, PCMCIA Interface.
For details, see section 11.4.3, CSn Bus Control Register (CSnBCR).
The bus width of the DDR-SDRAM and the PCI interfaces is 32 bits. For details, see section 12,
DDR-SDRAM Interface (DDRIF), and section 13, PCI Controller (PCIC).
The addresses of area 7 (H'1C00 0000 to H'1FFF FFFF) are reserved and must not be used.
Rev.1.00 Dec. 13, 2005 Page 324 of 1286
REJ09B0158-0100
Mode 4
Low
Low
High
High
Memory Bus Width
Mode 3
Low
High
Low
High
Bus Width
32 bits (For MPX interface)
8 bits
16 bits
32 bits (Other than MPX)

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