R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1074

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 27 NAND Flash Memory Controller (FLCTL)
Data Error:
• When a program error or erase error occurs, the error is reflected on the error source flags.
• When an ECC error is detected by software, perform an error correction, specify another sector
Data Transfer FIFO:
• The 224-byte FLDTFIFO is incorporated for data transfer of flash memory.
• The 32-byte FLECFIFO is incorporated for data transfer of a control code.
• Flag bit for detecting overrun/underrun during access from the CPU or DMA
DMA Transfer:
• By individually specifying the destinations of data and control code of flash memory to the
Access Size:
• Registers can be accessed in 32 bits or 8 bits. Registers must be accessed in the specified
• FIFOs are accessed in 32 bits (4 bytes). Set the byte number for read to a multiple of four, and
Access Time:
• The operating frequency of the FLCTL pins can be specified by the FCKSEL bit and the
• The operating clock FCLK on the pins for the NAND-type flash memory is generated by
• In NAND-type flash memory, the FRE and FWE pins operate with the frequency (FCLK) on
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Interrupts for each source can be specified.
to be replaced, and copy the contents of the block to another sector as required.
DMA controller, data and control code can be sent to different areas.
access size.
the byte number for write to a multiple of four.
QTSEL bit in the common control register (FLCMNCR), regardless of the operating frequency
of the peripheral bus.
dividing a peripheral clock (Pck).
the pins which common control register (FLCMNCR) designated. To ensure the setup time,
this operating frequencies must be specified within the maximum operating frequency of
memory to be connected.