R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1157

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29.2.1
CBR0 and CBR1 are readable/writable 32-bit registers which specify the break conditions for
channels 0 and 1, respectively. The following break conditions can be set in the CBR0 and CBR1:
(1) whether or not to include the match flag in the conditions, (2) whether or not to include the
ASID, and the ASID value when included, (3) whether or not to include the data value, (4)
operand size, (5) whether or not to include the execution count, (6) bus type, (7) instruction fetch
cycle or operand access cycle, and (8) read or write access cycle.
• CBR0
Bit
31
30
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Match Condition Setting Registers 0 and 1 (CBR0 and CBR1)
Bit Name
MFE
AIE
MFE
R/W
31
15
R
0
0
R/W
R/W
AIE
30
14
0
0
R/W
R/W
SZ
29
13
Initial
Value
0
0
1
0
R/W
R/W
28
12
0
0
R/W
27
11
R/W
R/W
R/W
R
0
0
MFI
R/W
26
10
R
0
0
Description
Match Flag Enable
Specifies whether or not to include the match flag value
specified by the MFI bit of this register in the match
conditions. When the specified match flag value is 1, the
condition is determined to be satisfied.
0: The match flag is not included in the match conditions;
1: The match flag is included in the match conditions.
ASID Enable
Specifies whether or not to include the ASID specified by
the AIV bit of this register in the match conditions.
0: The ASID is not included in the match conditions;
1: The ASID is included in the match conditions.
thus, not checked.
thus, not checked.
R/W
25
R
0
9
0
R/W
24
R
0
8
0
R/W
R/W
23
0
7
0
CD
Rev.1.00 Dec. 13, 2005 Page 1105 of 1286
R/W
R/W
22
0
6
0
Section 29 User Break Controller (UBC)
R/W
R/W
21
0
5
0
ID
R/W
R/W
20
0
4
0
AIV
R/W
19
R
0
3
0
R/W
R/W
REJ09B0158-0100
18
0
2
0
RW
R/W
R/W
17
0
1
0
R/W
R/W
CE
16
0
0
0