R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 79
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 79 of 1342
- Download datasheet (7Mb)
Section 1 Overview
1.5
Memory Address Map
The SH7780 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical
address spaces (normal mode and extended mode). For details of mappings from the virtual
address space to the physical address spaces, see section 7, Memory Management Unit (MMU).
The external memory space of the SH7780 consists of the LBSC space, DDRIF space and PCIC
space. The LBSC has up to 384 Mbytes, the DDRIF has up to 256 Mbytes and the PCIC has up to
512 Mbytes external memory space individually and the SH7780 can control the external memory
space up to 1152 Mbytes totally. Areas 0, 1, and 6 are controlled by the LBSC. Areas 2, 4, and 5
are controlled by the LBSC, DDRIF or PCIC that depends on the setting of the memory address
map select register (MMSELR) of the LBSC. Note that area 3 is for the DDRIF. For details, see
section 11, Local Bus Sate Controller (LBSC), section 12, DDR-SDRAM Interface (DDRIF) or
section 13, PCI Controller (PCIC).
Figure 1.3 shows the physical address space of the SH7780. Figure 1.4 shows the relationship
between the AREASEL bits and the memory address map. The 32-bit physical address space
corresponds with the address space of the SuperHyway bus.
Rev.1.00 Dec. 13, 2005 Page 27 of 1286
REJ09B0158-0100
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