PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 109

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

10.21.4 Clock Synthesis Unit (CSU)
10.22 JTAG Test Access Port Interface
10.23 Microprocessor Interface
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
The CSU is a fully integrated clock synthesis unit. It generates low jitter multi-phase differential
clocks at 777.6 MHz for the usage by the transmitter. The APFIFPCLK is used as a jitter-free
reference clock to the CSU.
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG
EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The
S/UNI-2488 identification code is 053810CD hexadecimal.
The Microprocessor Interface Block provides the logic required to interface the generic
microprocessor bus with the normal mode and test mode registers within the S/UNI-2488. The
normal mode registers are used during normal operation to configure and monitor the
S/UNI-2488. The test mode registers are used to enhance the testability of the S/UNI-2488. The
register set is accessed as shown below. The corresponding memory map address is identified by
the address column of the table. Addresses that are not shown are not used and must be treated as
Reserved.
Table 8 Register Memory Map
Address
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0011
0012
0013
Register Description
S/UNI-2488 Identity and Global Performance Monitor Update
S/UNI-2488 Master Reset, Configuration, and Loopback
S/UNI-2488 Transmit Control Register
S/UNI-2488 Clock Monitors
S/UNI-2488 Master Interrupt Status #1
S/UNI-2488 Master Interrupt Status #2
S/UNI-2488 Master Interrupt Status #3
S/UNI-2488 Master Interrupt Status #4
S/UNI-2488 Master Interrupt Status #5
S/UNI-2488 Master Interrupt Status #6
S/UNI-2488 Master Interrupt Status #7
Software General Purpose (FREE[12:0])
S/UNI-2488 APS Input TelecomBus Synchronization Delay
Reserved
S/UNI-2488 Diagnostics
S/UNI-2488 Identification Register
Rx2488 Analog Interrupt Status
Rx2488 Analog Interrupt Control
Rx2488 Analog CRU Control
Rx2488 Analog CRU Clock Training Configuration and Status
S/UNI-2488 Telecom Standard Product Datasheet
Released
109