PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 465

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0861H: T8TE APS1 Interrupt Status
Register 0869H: T8TE APS2 Interrupt Status
Register 0871H: T8TE APS3 Interrupt Status
Register 0879H: T8TE APS4 Interrupt Status
FIFOERRI
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The FIFO overrun/underrun error interrupt indication bit (FIFOERRI) reports a FIFO
overrun/underrun error event. FIFO overrun/underrun errors occur when FIFO logic detects
FIFO read and write pointers in close proximity to each other. FIFOERRI is set to logic 1 on
a FIFO overrun/underrun error. FIFOERRI is set to logic 0 when the T8TE Interrupt status
register is read. This bit does not cause a hardware interrupt on INTB unless the FIFOERRE
bit is set high. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
Type
R
Unused
Unused
Unused
Unused
Unused
Unused
FIFOERRI
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
Released
465