PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 511

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.1
13.1.1
13
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Operation
APS Serial TelecomBus (LVDS) Operation
LVDS Overview
The LVDS APS Port implements the 777.6 Mb/s LVDS links. Four 777.6 Mb/s LVDS form a
high-speed serial TelecomBus interface for passing an STS-48 aggregate data stream.
A reference clock of 77.76MHz is required via the APSIFPCLK pin. This clock must be an exact
divide-by-two of the REFCLK being provided to the chip. Do not use the TCLK or RCLK
outputs of the S/UNI-2488 as they are not reliable enough to provide this reference and are not
intended for this purpose.
A generic LVDS link according to IEEE 1596.3-1996 is illustrated below. The transmitter drives
a differential signal through a pair of 50W characteristic interconnects, such as board traces,
backplane traces, or short lengths of cable. The receiver presents a 100W differential termination
impedance to terminate the lines. Included in the standard is sufficient common-mode range for
the receiver to accommodate as much as 925mV of common-mode ground difference.
Figure 24 Generic LVDS Link Block Diagram
Complete SERDES transceiver functionality is provided. Ten-bit parallel data is sampled by the
line rate divided-by-10 clock (77.76MHz APSIFPCLK) and then serialized at the line rate on the
LVDS output pins by a 777.6MHz clock synthesized from a divided version of REFCLK. Serial
line rate LVDS data is sampled and de-serialized to 10-bit parallel data. Parallel output transfers
are synchronized to a gated line rate divided-by-10 clock. The 10-bit data is passed to an 8B/10B
decoding block. The gating duty cycle is adjusted such that the throughput of the parallel
interface equals the receive input data rate (Line Rate +/- 100ppm). It is expected that the clock
source of the transmitter is the same as the clock source of the receiver to ensure the data
throughput at both ends of the link are identical.
Transmitter
V
V
op
on
Interconnect
Zo=50
Zo=50
S/UNI-2488 Telecom Standard Product Datasheet
V
V
ip
in
Receiver
Released
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