PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 59

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Pin Name
RPRTY
RDAT[31]
RDAT[30]
RDAT[29]
RDAT[28]
RDAT[27]
RDAT[26]
RDAT[25]
RDAT[24]
RDAT[23]
RDAT[22]
RDAT[21]
RDAT[20]
RDAT[19]
RDAT[18]
RDAT[17]
RDAT[16]
RDAT[15]
RDAT[14]
RDAT[13]
RDAT[12]
Type
Output
Output
Pin
No.
P29
D30
E29
F28
G27
E30
F29
G28
H27
F30
H28
J27
G30
H29
J28
H30
J29
K28
L27
J30
L28
Function
The POS-PHY receive FIFO read clock (RFCLK) signal is
used to read packet data from the receive packet FIFO.
RFCLK is expected to cycle at 104 MHz.
The UTOPIA receive parity (RPRTY) signal indicates the
parity of the RDAT[31:0] bus. Odd or even parity may be
selected.
RPRTY is valid only when RENB has been sampled low in the
previous clock cycle.
RPRTY is updated on the rising edge of RFCLK.
The POS-PHY receive parity (RPRTY) signal indicates the
parity of the RDAT[31:0] bus. Odd or even parity may be
selected.
RPRTY is valid only when either RVAL or RSX are asserted.
RPRTY is updated on the rising edge of RFCLK.
The UTOPIA receive cell data (RDAT[31:0]) bus carries the
ATM cell octets that are read from the receive FIFO.
RDAT[31:0] is updated on the rising edge of RFCLK.
S/UNI-2488 Telecom Standard Product Datasheet
Released
59