PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 470

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
ATIN[3:0]
APISO_ENB
TXLV_ENB
IDDQ
The analog test control inputs (ATIN[3:0]) control the APISO and TXLV test circuitry. These
bits are not used for normal operation.
The APISO enable bit (APISO_ENB) controls the APISO operation. When set to logic 1,
APISO_ENB disables the APISO. When set to logic 0, APISO_ENB enables the APISO.
APISO_ENB should be set to logic 1 to conserve power consumption for applications not
using the APS port.
The TXLV enable bit (TXLV_ENB) controls the TXLV operation. When set to logic 1,
TXLV_ENB disables the TXLV. When set to logic 0, TXLV_ENB enables the TXLV.
TXLV_ENB should be set to logic 1 to conserve power consumption for applications not
using the APS port.
The IDDQ controls the APISO operation. When IDDQ is set high, IDDQ test of the APISO
is enabled. For normal operation, IDDQ should be set low.
S/UNI-2488 Telecom Standard Product Datasheet
Released
470