PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 372

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0747H: RCFP Receive Byte/Idle Cell Counter (LSB)
Register 0748H: RCFP Receive Byte/Idle Cell Counter
Register 0749H: RCFP Receive Byte/Idle Cell Counter (MSB)
RBY_IC[39:0]
A write to any one of the RCFP performance monitor counter registers loads the registers with the
current counter value and resets the internal 40 bit counter to 4,3,2,1 or 0. The counter reset value
is dependent on if there were counter events during the transfer of the count to RCFP
performance monitor Counter registers. The counter should be polled regularly to avoid
saturation.
To allow for synchronization update with all other blocks, writing to register 0000H will initiate a
global performance counter update.
Bit
Bit 15
to
Bit 0
Bit
Bit 15
to
Bit 0
Bit
Bit 15
to
Bit 8
Bit 7
to
Bit 0
When POS mode is selected, the RBY_IC[39:0] bits indicate the number of bytes received
within POS frames during the last accumulation interval. The byte counts include all user
payload bytes, FCS bytes, and abort bytes. Inclusion of stuffed bytes in the count is
controlled by the RBY_MODE register bit. HDLC flags are not counted. In either mode, an
abort sequence (0x7d7e) is counted as one byte.
When ATM mode is selected, the RBY_IC[39:0] bits indicate the number of Idle cells
received and passed to the FIFO interface in the last accumulation interval.
Type
R
Type
R
Type
R
RBY_IC[15:0]
RBY_IC[31:16]
Unused
RBY_IC[39:32]
Function
Function
Function
S/UNI-2488 Telecom Standard Product Datasheet
Default
XXXX
Default
XXXX
Default
XXXX
XXXX
Released
372