PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 532

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.12.2 TPAHOLD = 1
TDAT[31:0]
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TMOD[1:0]
TFCLK
TPRTY
TENB
TSOP
TEOP
TERR
DTPA
Figure 30 shows the behavior of DTPA when the TPAHOLD register bit (in register 788H
TXPHY Configuration) is set to logic 1. This is the optional operating mode which decreases the
DTPA response delay from 5 cycles to 1 cycle. This optional mode is only usable when each
burst is terminated by a TENB transition to logic 1. Once a burst has been allowed by polling
DTPA at logic 1, then one full burst is allowed. DTPA must be polled at logic 1 again before
another burst can be started.
In this example, the write to the FIFO which occurs at the start of cycle 7 crosses the TXSDQ’s
BT[4:0] threshold. DTPA responds on cycle 8. There is a 1 clock cycle delay between the write
and the response on DTPA.
The TXSDQs FIFO threshold must be set-up differently. For this mode to operate correctly:
·
While the TXSDQ’s FIFO threshold is set so it transitions when less than 2 bursts remain
available, the TPAHOLD feature will hold DTPA high until there is less than 1 burst available.
Thus, the user can still fully utilize the entire FIFO.
Because we usually want the TXSDQ’s data threshold (DT[7:0]) to be a fairly large value to
prevent FIFO underruns, the burst-size must be set to a reasonable value (see Section 13.7 for
restrictions on the relationship between TXSDQ’s DT[7:0] and BT[4:0]).
Figure 30 TPAHOLD Set To 1
BT[4:0] = 2*burst-size – 1
Where burst-size is in units of blocks (1 block = 16 bytes).
1
1000
B1-B4
2
3
4
5
1000
B1-B4
6
S/UNI-2488 Telecom Standard Product Datasheet
B5-B8
7
B9-B12
8
B13-B16
9
B17-B20
10
B21-B24
11
Released
B25-B28
12
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