PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 52

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

9.1
9
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Pin Description
Serial Line Side Interface Signals (7)
Pin Name
REFCLK_P
REFCLK_N
RXD_P
RXD_N
SD
TXD_P
TXD_N
Type
Differential
PECL -
compatible
Input
Differential
PECL-
compatible
Input
TTL
Input
Differential,
CML -
compatible
Output
Pin
No.
AK10
AK9
AK16A
K15
AH24
AK12
AK13
Function
The differential reference clock inputs (REFCLK_P /
REFCLK_N) provides a 155.52 MHz reference clock for both
the clock recovery and the clock synthesis circuits. The two
PECL inputs are internally terminated with differential 100-W
termination.
In practice, jitter on REFCLK_P / REFCLK_N inputs must be
less than 1 psec RMS in 12KHz to 20MHz band in order for
S/UNI2488 to comply with Bellcore GR-253 intrinsic jitter
specs on transmit data outputs.
Note: Any jitter on REFCLK_P / REFCLK_N up to about 20
MHz will also appear at the transmit data output.
Please refer to the Operation section for a discussion of PECL
interfacing issues.
The receive differential data PECL-compatible inputs
(RXD_P/ RXD_N) contain the 2488.32 Mbit/s NRZ bit serial
receive stream. The two receive inputs are internally
terminated with differential 100-W termination. The receive
clock is recovered from the RXD_P/ RXD_N bit stream.
Please refer to the Operation section for a discussion of PECL
interfacing issues.
The receive signal detect TTL input (SD) indicates the
presence of valid receive signal power from the Optical
Physical Medium Dependent Device. A logic high indicates
the presence of valid data. A logic low indicates a loss of
signal.
Unless SD detection is disabled, deassertion of SD will cause
the 2488 CRU to go into training mode where it locks to
REFCLK_P/REFCLK_N.
Please refer to the Operation section for a discussion of
interfacing issues
The transmit differential data CML-compatible outputs
(TXD_P/ TXD_N) contain the 2488.32 Mbit/s transmit stream.
The TXD_P/ TXD_N outputs are driven using the synthesized
clock from the CSU.
Please refer to the Operation section for a discussion of the
voltage swing levels.
S/UNI-2488 Telecom Standard Product Datasheet
Released
52