PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 425

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0788H: TXPHY Configuration
All Reserved bits must be set to their default values for proper operation.
TXPRST
ODDPARITY
PARERREN
Reserved0
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The TXPRST bit is used to reset the TXPHY circuitry. When TXPRST is set to logic zero,
the TXPHY operates normally. When TXPRST is set to logic one, the TXPHY ignores all
pin inputs but the registers may be accessed for initialization. The TXPHY deasserts all
outputs until a logic zero is written to TXPRST.
The ODDPARITY bit is used to set the type of parity that is checked by the TXPHY. When
set to logic 1, odd parity is expected. When set to logic 0, even parity is expected.
When set to logic 1, PARERREN will enable the TXPHY to pass an error signal to the
TXSDQ upon detection of a parity error. This will cause the packet to be aborted by the
packet processor. This bit has no effect on ATM cells with parity errors. This bit must be set
while TXPRST is logic one.
This bit must be set to logic 0 for proper operation.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved0
Reserved
Reserved
PARERREN
Reserved
ODDPARITY
TXPRST
TPAHOLD
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
0
0
0
1
0
0
0
0
0
1
Released
425