PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 276

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
PAISCI
The path concatenation alarm indication signal interrupt status (PAISCI) bit is an event
indicator. PAISCI is set to logic 1 to indicate any change in the status of PAISCV (entry to
the AISC_state or exit from the AISC_state). The interrupt status bit is independent of the
interrupt enable bit. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this
bit. If WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
This bit is only valid for RHPP STS-1/STM0 #2-48 except in the XCONNECT mode of
operation.
S/UNI-2488 Telecom Standard Product Datasheet
Released
276