PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 48

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Description
The PM5381 S/UNI-2488 SATURN User Network Interface is a monolithic integrated circuit that
implements SONET/SDH processing, ATM mapping and Packet over SONET mapping functions
at the STS-48 (STM-16-16c) 2488.32 Mbit/s rate.
The S/UNI-2488 receives SONET/SDH streams using a bit serial interface, recovers the clock
and data and processes section, line, and path overhead. The S/UNI-2488 performs framing (A1,
A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved
parity (B1, B2, B3), accumulating error counts at each level for performance monitoring
purposes. Line and path remote error indications (M1, G1) are also accumulated. The S/UNI-
2488 interprets the received payload pointers (H1, H2) and extracts the synchronous payload
envelope which carries the received ATM cells or POS frames.
When used to implement an ATM UNI or NNI, the S/UNI-2488 frames to the ATM payload using
cell delineation. Idle/unassigned cells may be optionally dropped. Cells are also dropped upon
detection of a header check sequence error. The ATM cell payloads are descrambled and are
written to a 48-cell FIFO buffer (programmable FIFO depth). The received cells are read from
the FIFO using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz) datapath interface.
Counts of received ATM cell headers that are erroneous are accumulated independently for
performance monitoring purposes.
When used to implement packet transmission over a SONET/SDH link, the S/UNI-2488 extracts
Packet over SONET (POS) frames from the SONET/SDH synchronous payload envelope.
Frames are verified for correct construction and size. The control escape characters are removed.
The frame check sequence is optionally verified for correctness and the extracted packets are
placed in a receive 192x16-byte FIFO (programmable FIFO depth – all packets are 16 byte block
aligned). The received packets are read from the FIFO through a 32-bit POS-PHY Level 3
(clocked up to 104 MHz) system side interface. Valid packet and erroneous packet counts are
provided for performance monitoring. The S/UNI-2488 Packet over SONET implementation is
flexible enough to support several link layer protocols, including HDLC, PPP and Frame Relay.
The S/UNI-2488 transmits SONET/SDH streams using a bit serial interface. The S/UNI-2488
synthesizes the transmit clock from a 155.52MHz frequency reference and performs framing
pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path
bit interleaved parity codes (B1, B2, B3) as required to allow performance monitoring at the far
end. Line and path remote error indications (M1, G1) are also inserted. The S/UNI-2488
generates the payload pointer (H1, H2) and inserts the synchronous payload envelope that carries
the ATM or POS frames. The S/UNI-2488 also supports the insertion of a large variety of errors
into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal
pointers, which are useful for system diagnostics and tester applications.
When used to implement an ATM UNI or NNI, ATM cells are written to an internal 48 cell FIFO
(programmable FIFO depth) using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz)
datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO
contains less than one complete cell. The S/UNI-2488 provides generation of the header check
sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell
processing functions can be enabled or bypassed.
S/UNI-2488 Telecom Standard Product Datasheet
Released
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