PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 360

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
CRC_SEL[1:0]
CRCPASS
The CRC select (CRC_SEL[1:0]) bits control the CRC calculation according to the table
below. For ATM cells, the CRC is calculated over the first four ATM header bytes. For
packet applications, the CRC is calculated over the whole packet data, after byte destuffing
and descrambling.
Table 12 Functionality of the CRC_SEL[1:0] Register Bits
The CRCPASS bit controls the dropping of cells and packets based on the detection of an
incorrect CRC.
When in ATM mode and when CRCPASS is a logic 0, cells containing an HCS error are
dropped.
When CRCPASS is logic 1, cells are passed to the external FIFO interface regardless of
errors detected in the HCS. Additionally, the Cell Delineation finite state machine never exits
the SYNC state, and hence will never lose cell delineation. Note that HCS errors are still
counted.
Note that ATM idle cells that contain HCS errors will cause the state machine to change state
regardless of the setting of the IDLEPASS register bit.
When in POS mode and CRCPASS is logic 1, packets with FCS errors are not marked as
such and are passed to the external FIFO interface as if no FCS error occurred. When
CRCPASS is logic 0, then packets with FCS errors are marked using FIFO_ERR[x] on the
EOP byte.
Regardless of the programming of this bit, ATM cells are always dropped while the cell
delineation state machine is in the 'HUNT' or 'PRESYNC' states unless the DELINDIS bit in
this register is set to logic 1.
CRC_SEL[1:0]
00
01
10
11
HCS Operation
Reserved
Reserved
CRC-8 without coset polynomial
CRC-8 with coset polynomial added
S/UNI-2488 Telecom Standard Product Datasheet
FCS Operation
Reserved
Reserved
CRC-CCITT (2 bytes)
CRC-32 (4 bytes)
Released
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