PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 168

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0021H: TX2488 ABC Control
CSU_MODE[7:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The CSU Mode control bits are used to place the CSU in one of the following operating
modes:
Table 11 CSU Mode Control
Mode Bits
7
6:5
4
R/W
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CSU Input reference clock selection bit:
Loop filter resistor select. They allow selection of various loop filter
parameters that affect bandwidth. Selection modes are:
Bits 6:5 Resistor Value
Note: The optimum resistor for PFD mode is 12.5kW. The optimum
resistor for Hogge-II mode is 10kW. The optimum resistor for loop-
timed operation is 2.5kW. See CSU_MODE[2] register bit
description also.
Reserved
10
00
11
01
0 – CRU Recovered Clock (loop-time)
1 – External Reference Clock (lock to reference)
Function
Reserved
PISO_RESET
CSU_RESET
RX_REF ENABLE
TX2488_ENABLE
C2C_ENABLE
Reserved1
IDDQ_ENABLE
CSU_MODE[7]
CSU_MODE[6]
CSU_MODE[5]
CSU_MODE[4]
CSU_MODE[3]
CSU_MODE[2]
CSU_MODE[1]
CSU_MODE[0]
2 x 2.5kW (reduces bandwidth for loop-timed operation)
2 x 12.5kW (increases bandwidth of CSU by 25% compared
2 x 10kW (Default)
Reserved
to default)
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
Released
168