PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 146

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 000CH: APS Input TelecomBus Synchronization Delay
This register controls the delay from the APSIFP input signal to the time when the S/UNI-2488
may safely process the J0 characters delivered by the APS Input serial data links (APSI_P/
APSI_N[4:1]).
AIJ0DLY[13:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The APS Input transport frame delay bits (AIJ0FP[13:0]) controls the delay, in APSIFPCLK
cycles, inserted by the S/UNI-2488 before processing the J0 characters delivered by the APS
Input serial data links (APSI_P/ APSI_N[4:1]). AIJ0DLY is set such that after the specified
delay, all active APS Input links would have delivered the J0 character. The relationships of
AIJ0FP, AIJ0DLY[13:0] and the system configuration are described in the Functional Timing
section.
Valid values of AIJ0DLY[13:0] are 0000H to 25F7H.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unused
Unused
AIJ0DLY[13]
AIJ0DLY[12]
AIJ0DLY[11]
AIJ0DLY[10]
AIJ0DLY[9]
AIJ0DLY[8]
AIJ0DLY[7]
AIJ0DLY[6]
AIJ0DLY[5]
AIJ0DLY[4]
AIJ0DLY[3]
AIJ0DLY[2]
AIJ0DLY[1]
AIJ0DLY[0]
Function
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Released
146