PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 574

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Table 35 Microprocessor Interface Write Access Timing (Figure 54)
Figure 54 Intel Microprocessor Interface Write Timing
Notes on Microprocessor Interface Write Timing:
1.
2.
3.
4.
5.
Symbol
tS
tS
tS
tH
tV
tS
tH
tH
tH
tV
TZ
aw
dw
alw
l
lw
wr
alw
lw
dw
aw
winth
(CSB+WRB)
A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS alw ,
tH alw , tV l , tS lw , and tH lw are not applicable.
Parameter tH aw is not applicable if address latching is used.
When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 Volt point of the input to the 1.4 Volt
A[13:0]
D[15:0]
INTB
ALE
Parameter
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Write Set-up
Latch to Write Hold
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
Valid Write Negated to INTB High (WCIMODE =
1)
tSalw
tVl
tVl
tSaw
tSlw
S/UNI-2488 Telecom Standard Product Datasheet
tHalw
tVwr
tVwr
tSdw
VALID
Min
10
20
10
10
5
0
10
5
10
40
tHaw
tHdw
tZwinth
tHlw
Max
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Released
574