PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 254

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
PRDI10
FSBIPDIS
PBIPEBLKACC
PBIPECNTBLK
B3EBLK
PREIBLKACC
The path remote defect indication detection (PRDI10) bit selects the path RDI and path ERDI
persistence. When PRDI10 is set to logic 1, path RDI and path ERDI are accepted when the
same pattern is detected in bits 5,6,7 of the G1 byte for ten consecutive frames. When
PRDI10 is set to logic 0, path RDI and path ERDI are accepted when the same pattern is
detected in bits 5,6,7 of the G1 byte for five consecutive frames.
The disable fixed stuff columns during BIP-8 calculation (FSBIPDIS) bit controls the path
BIP-8 calculation for an STS-1 (VC-3) payload. When FSBIPDIS is set to logic 1, the fixed
stuff columns are not part of the BIP-8 calculation when processing an STS-1 (VC-3)
payload. When FSBIPDIS is set to logic 0, the fixed stuff columns are part of the BIP-8
calculation when processing an STS-1 (VC-3) payload.
The path block BIP-8 errors accumulation (PBIPEBLKACC) bit controls the accumulation of
path BIP-8 errors. When PBIPEBLKACC is set to logic 1, the path BIP-8 error accumulation
represents block BIP-8 errors (a maximum of 1 error per frame). When PBIPEBLKACC is
set to logic 0, the path BIP-8 error accumulation represents BIP-8 errors (a maximum of 8
errors per frame).
The path block BIP-8 errors count (PBIPECNTBLK) bit controls the way path BIP-8 errors
are reported to the SARC. If PBIPECNTBLK is set to logic 1, BIP-8 errors are counted on a
block basis, incremented only once for one or more BIP-8 errors. When PBIPECNTBLK is
set to logic 0, the number of incorrect bits in the BIP-8 are reported (maximum of 8).
The serial path block BIP-8 errors count (B3EBLK) bit controls the way path BIP-8 errors are
reported via the RPOH extract pin. If B3EBLK is set to logic 1, BIP-8 errors are counted on
a block basis, incremented only once for one or more BIP-8 errors. When B3EBLK is set to
logic 0, the number of incorrect bits in the BIP-8 are reported (maximum of 8).
The path block REI errors accumulation (PREIBLKACC) bit controls the accumulation of
path REI errors from the path status (G1) byte. When PREIBLKACC is set to logic 1, the
extracted path REI errors are interpreted as block BIP-8 errors (a maximum of 1 error per
frame). When PREIBLKACC is set to logic 0, the extracted path REI errors are interpreted
as BIP-8 errors (a maximum of 8 errors per frame).
S/UNI-2488 Telecom Standard Product Datasheet
Released
254